hdlmake.tools.libero package¶
Module contents¶
Module providing support for Microsemi Libero IDE synthesis
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class
hdlmake.tools.libero.
ToolLibero
¶ Bases:
hdlmake.tools.make_syn.ToolSyn
Class providing the interface for Microsemi Libero IDE synthesis
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CLEAN_TARGETS
= {'clean': ['$(PROJECT)'], 'mrproper': ['*.pdb', '*.stp']}¶
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HDL_FILES
= {<class 'hdlmake.srcfile.VHDLFile'>: 'create_links -hdl_source $(sourcefile)', <class 'hdlmake.srcfile.VerilogFile'>: 'create_links -hdl_source $(sourcefile)'}¶
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STANDARD_LIBS
= ['ieee', 'std']¶
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SUPPORTED_FILES
= {<class 'hdlmake.srcfile.SDCFile'>: 'create_links -sdc $(sourcefile)', <class 'hdlmake.srcfile.PDCFile'>: 'create_links -pdc $(sourcefile)'}¶
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TCL_CONTROLS
= {'bitstream': '$(TCL_OPEN)\nupdate_and_run_tool -name {GENERATEPROGRAMMINGDATA}\n$(TCL_SAVE)\n$(TCL_CLOSE)', 'close': 'close_project', 'create': 'new_project -location {{./{0}}} -name {{{0}}} -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}} -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}', 'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb', 'open': 'open_project -file {$(PROJECT)/$(PROJECT_FILE)}', 'project': '$(TCL_CREATE)\nsource files.tcl\n{0}\n$(TCL_SAVE)\n$(TCL_CLOSE)', 'save': 'save_project'}¶
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TOOL_INFO
= {'id': 'libero', 'linux_bin': 'libero SCRIPT:', 'name': 'Libero', 'project_ext': 'prjx', 'windows_bin': 'libero.exe SCRIPT:'}¶
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