hdlmake package

Subpackages

• hdlmake.action package
  • Submodules
  • hdlmake.action.action module
  • hdlmake.action.core module
  • hdlmake.action.tree module
  • hdlmake.action.qsys_hw_tcl_update module
  • Module contents
• hdlmake.fetch package
  • Submodules
  • hdlmake.fetch.backend_factory module
  • hdlmake.fetch.constants module
  • hdlmake.fetch.fetcher module
  • hdlmake.fetch.git module
  • hdlmake.fetch.svn module
  • Module contents
• hdlmake.tools package
  • Subpackages
    • hdlmake.tools.active_hdl package
      • Module contents
    • hdlmake.tools.sim_makefile_support package
      • Module contents
    • hdlmake.tools.diamond package
      • Module contents
    • hdlmake.tools.ghdl package
      • Module contents
    • hdlmake.tools.ise package
      • Module contents
    • hdlmake.tools.isim package
      • Module contents
    • hdlmake.tools.iverilog package
      • Module contents
    • hdlmake.tools.libero package
      • Module contents
    • hdlmake.tools.modelsim package
      • Module contents
    • hdlmake.tools.planahead package
      • Module contents
    • hdlmake.tools.quartus package
      • Module contents
    • hdlmake.tools.riviera package
      • Module contents
    • hdlmake.tools.vivado package
      • Module contents
  • Module contents
• hdlmake.util package
  • Submodules
  • hdlmake.util.path module
  • hdlmake.util.termcolor module
  • Module contents

Submodules

hdlmake.dep_file module

Module providing the Classes used to provide and handle dependable files

class hdlmake.dep_file.DepFile(file_path, module)

Bases: hdlmake.dep_file.File

Class that serves as base to all those HDL files that can be parsed and solved (Verilog, SystemVerilog, VHDL)

add_relation(rel)

Add a new relation to the set provided by the file

filename

Property defined as a method that checks the basename of the file path in the host, i.e. the name of the last directory on the path

get_dep_level()

Get the dependency level for the file instance, so we can order later the full fileset

satisfies(rel_b)

Check if any of the file object relations match any of the relations listed in the parameter (rel_b)

show_relations()

Print the file relations to stdout: can be used for logging

class hdlmake.dep_file.DepRelation(obj_name, direction, rel_type)

Bases: object

Class used to create instances representing HDL dependency relations

ARCHITECTURE = 4

ENTITY = 1

INCLUDE = 3

MODULE = 1

PACKAGE = 2

PROVIDE = 1

USE = 2

library()

If the current relation type is PACKAGE, it returns the base name of the library, e.g. for work.counter it returns work.

satisfies(rel_b)

Check if the current dependency relation matches the provided one

class hdlmake.dep_file.File(path, module=None)

Bases: object

This is the base class for all of the different files in HDLMake

dirname

Property defined as a method that gets the name of the directory in which the file is stored

extension()

Method that gets the extension for the file instance

isdir()

Check if the defined file path is a directory

name

Property defined as a method that gets the basename of the file path, i.e. it strips the path and takes the full file name

purename

Property defined as a method that gets the name of the file and strips put the extension from the file

rel_path(directory=None)

Returns the relative path for the file calculated with (directory) as the origin reference – if none, it will be defaulted to current folder from which we are launching the program

show()

Print the file path to stdout

hdlmake.new_dep_solver module

This package provides the functions and classes to parse and solve HDLMake filesets

class hdlmake.new_dep_solver.DepParser(dep_file)

Bases: object

Base Class for the different HDL parsers (VHDL and Verilog)

parse(dep_file)

Base dummy interface method for the HDL parse execution

hdlmake.new_dep_solver.make_dependency_set(fileset, top_level_entity, extra_modules=None)

Create the set of all files required to build the named top_level_entity.

hdlmake.new_dep_solver.make_dependency_sorted_list(fileset, reverse=False)

Sort files in order of dependency. Files with no dependencies first. All files that another depends on will be earlier in the list.

hdlmake.new_dep_solver.solve(fileset, standard_libs=None)

Function that Parses and Solves the provided HDL fileset. Note that it doesn’t return a new fileset, but modifies the original one

hdlmake.env module

Package providing the bridge with the Host O.S. environment

class hdlmake.env.Env(options)

Bases: dict

The Env (Environment) is a dictionary containing the environmental variables related with HDLMake for a proper use in the Python code

hdlmake.manifest_parser module

Python Package providing the Manifest.py parser for HDLMake

hdlmake.module module

Package providing the Module functionality to HDLMake

hdlmake.module_pool module

This is the Python module providing the container for the HDL Modules

class hdlmake.module_pool.ModulePool(*args)

Bases: hdlmake.action.core.ActionCore, hdlmake.action.tree.ActionTree

The ModulePool class acts as the container for the HDLMake modules that are progressively being added to the design hierarchy.

hdlmake.srcfile module

Module providing the source file class and a set of classes representing the different possible files and file extensions

class hdlmake.srcfile.BDFFile(path, module=None)

Bases: hdlmake.dep_file.File

Quartus Block Design File

class hdlmake.srcfile.BDFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Block Design

class hdlmake.srcfile.BMMFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Block Memory Map File

class hdlmake.srcfile.BSFFile(path, module=None)

Bases: hdlmake.dep_file.File

Quartus Block Symbol File

class hdlmake.srcfile.CDCFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the Xilinx ChipScope Definition and Connection file

class hdlmake.srcfile.COEFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Coefficient File

class hdlmake.srcfile.DPFFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing Altera Quartus Design Protocol File

class hdlmake.srcfile.EDFFile(path, module=None)

Bases: hdlmake.dep_file.File

EDIF Netlist Files

class hdlmake.srcfile.GDFFile(path, module=None)

Bases: hdlmake.dep_file.File

Quartus Graphic Design File

class hdlmake.srcfile.LDFFile(path, module=None)

Bases: hdlmake.dep_file.File

Lattice Diamond Project File

class hdlmake.srcfile.LPFFile(path, module=None)

Bases: hdlmake.dep_file.File

Lattice Preference/Constraint File

class hdlmake.srcfile.MIFFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Memory Initialization File

class hdlmake.srcfile.NGCFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Generated Netlist File

class hdlmake.srcfile.PCFFile(path, module=None)

Bases: hdlmake.dep_file.File

Icestorm Physical constraints File

class hdlmake.srcfile.PDCFile(path, module=None)

Bases: hdlmake.dep_file.File

Physical Design Constraints

class hdlmake.srcfile.PPRFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx PlanAhead Project

class hdlmake.srcfile.QIPFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the Altera Quartus IP file

class hdlmake.srcfile.QSFFile(path, module=None)

Bases: hdlmake.dep_file.File

Quartus Settings File

class hdlmake.srcfile.QSYSFile(path, module=None)

Bases: hdlmake.dep_file.File

Qsys - Altera’s System Integration Tool

class hdlmake.srcfile.RAMFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx RAM File

class hdlmake.srcfile.SDCFile(path, module=None)

Bases: hdlmake.dep_file.File

Synopsys Design Constraints

class hdlmake.srcfile.SVFile(path, module, library=None, include_dirs=None, is_include=False)

Bases: hdlmake.srcfile.VerilogFile

This is the class providing the generic SystemVerilog file

class hdlmake.srcfile.SignalTapFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the Altera Signal Tap Language file

class hdlmake.srcfile.SourceFile(path, module, library)

Bases: hdlmake.dep_file.DepFile

This is a class acting as a base for the different HDL sources files, i.e. those that can be parsed

cur_index = 0

class hdlmake.srcfile.SourceFileSet

Bases: set

Class providing a extension of the ‘set’ object that includes methods that allow for an easier management of a collection of HDL source files

add(files)

Add a set of files to the source fileset instance

filter(filetype)

Method that filters and returns all of the HDL source files contained in the instance SourceFileSet matching the provided type

get_libs()

Method that returns a set containing all of the libraries that are provided by any of the source files in the SourceFileSet

inversed_filter(filetype)

Method that filters and returns all of the HDL source files contained in the instance SourceFileSet NOT matching the provided type

class hdlmake.srcfile.TCLFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the Tool Command Language file

class hdlmake.srcfile.TDFFile(path, module=None)

Bases: hdlmake.dep_file.File

Quartus Text Design File

class hdlmake.srcfile.UCFFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the User Constraint Guide file

class hdlmake.srcfile.VEOFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Verilog Template File

class hdlmake.srcfile.VHDLFile(path, module, library=None)

Bases: hdlmake.srcfile.SourceFile

This is the class providing the generic VHDL file

class hdlmake.srcfile.VHOFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx VHDL Template File

class hdlmake.srcfile.VerilogFile(path, module, library=None, include_dirs=None, is_include=False)

Bases: hdlmake.srcfile.SourceFile

This is the class providing the generic Verilog file

class hdlmake.srcfile.WBGenFile(path, module=None)

Bases: hdlmake.dep_file.File

Wishbone generator file

class hdlmake.srcfile.XCFFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx XST Constraint File

class hdlmake.srcfile.XCIFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Core IP File

class hdlmake.srcfile.XCOFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Core Generator File

class hdlmake.srcfile.XDCFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Design Constraint File

class hdlmake.srcfile.XISEFile(path, module=None)

Bases: hdlmake.dep_file.File

This is the class providing the new Xilinx ISE project file

class hdlmake.srcfile.XMPFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Embedded Micro Processor

class hdlmake.srcfile.XPRFile(path, module=None)

Bases: hdlmake.dep_file.File

Xilinx Vivado Project

hdlmake.srcfile.create_source_file(path, module, library=None, include_dirs=None, is_include=False)

Function that analyzes the given arguments and returns a new HDL source file of the appropriated type

hdlmake.vhdl_parser module

Module providing the VHDL parser capabilities

class hdlmake.vhdl_parser.VHDLParser(dep_file)

Bases: hdlmake.new_dep_solver.DepParser

Class providing the container for VHDL parser instances

parse(dep_file)

Parse the provided VHDL file and add the detected relations to it

hdlmake.vlog_parser module

This module provides the Verilog parser for HDLMake

class hdlmake.vlog_parser.VerilogParser(dep_file)

Bases: hdlmake.new_dep_solver.DepParser

Class providing the Verilog Parser functionality

add_search_path(path)

Add a new candidate path to the Verilog preprocessor list containing the include dir candidates

parse(dep_file)

Parse the provided Verilog file and add to its properties all of the detected dependency relations

reserved_words = ['accept_on', 'alias', 'always', 'always_comb', 'always_ff', 'always_latch', 'assert', 'assign', 'assume', 'automatic', 'before', 'begin', 'bind', 'bins', 'binsof', 'bit', 'break', 'buf', 'bufif0', 'bufif1', 'byte', 'case', 'casex', 'casez', 'cell', 'chandle', 'checker', 'class', 'clocking', 'cmos', 'config', 'const', 'constraint', 'context', 'continue', 'cover', 'covergroup', 'coverpoint', 'cross', 'deassign', 'default', 'defparam', 'disable', 'dist', 'do', 'edge', 'else', 'end', 'endcase', 'endchecker', 'endclass', 'endclocking', 'endconfig', 'endfunction', 'endgenerate', 'endgroup', 'endinterface', 'endmodule', 'endpackage', 'endprimitive', 'endprogram', 'endproperty', 'endsequence', 'endspecify', 'endtable', 'endtask', 'enum', 'event', 'eventually', 'expect', 'export', 'extends', 'extern', 'final', 'first_match', 'for', 'force', 'foreach', 'forever', 'fork', 'forkjoin', 'function', 'generate', 'genvar', 'global', 'highz0', 'highz1', 'if', 'iff', 'ifnone', 'ignore_bins', 'illegal_bins', 'implies', 'import', 'incdir', 'include', 'initial', 'inout', 'input', 'inside', 'instance', 'int', 'integer', 'interface', 'intersect', 'join', 'join_any', 'join_none', 'large', 'let', 'liblist', 'library', 'local', 'localparam', 'logic', 'longint', 'macromodule', 'matches', 'medium', 'modport', 'module', 'nand', 'negedge', 'new', 'nexttime', 'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'null', 'or', 'output', 'package', 'packed', 'parameter', 'pmos', 'posedge', 'primitive', 'priority', 'program', 'property', 'protected', 'pull0', 'pull1', 'pulldown', 'pullup', 'pulsestyle_ondetect', 'pulsestyle_onevent', 'pure', 'rand', 'randc', 'randcase', 'randsequence', 'rcmos', 'real', 'realtime', 'ref', 'reg', 'reject_on', 'release', 'repeat', 'restrict', 'return', 'rnmos', 'rpmos', 'rtran', 'rtranif0', 'rtranif1', 's_always', 'scalared', 'sequence', 's_eventually', 'shortint', 'shortreal', 'showcancelled', 'signed', 'small', 's_nexttime', 'solve', 'specify', 'specparam', 'static', 'string', 'strong', 'strong0', 'strong1', 'struct', 's_until', 'super', 'supply0', 'supply1', 'sync_accept_on', 'sync_reject_on', 'table', 'tagged', 'task', 'this', 'throughout', 'time', 'timeprecision', 'timeunit', 'tran', 'tranif0', 'tranif1', 'tri', 'tri0', 'tri1', 'triand', 'trior', 'trireg', 'type', 'typedef', 'union', 'unique', 'unique0', 'unsigned', 'until', 'until_with', 'untypted', 'use', 'var', 'vectored', 'virtual', 'void', 'wait', 'wait_order', 'wand', 'weak', 'weak0', 'weak1', 'while', 'wildcard', 'wire', 'with', 'within', 'wor', 'xnor', 'xor']

class hdlmake.vlog_parser.VerilogPreprocessor

Bases: object

This class provides the Verilog Preprocessor

class VLDefine(name, args, expansion)

Bases: object

Class that provides a container for Verilog Defines

class VLStack

Bases: object

Class that provides a simple binary (true/false) stack for Verilog Defines for nested `ifdefs evaluation

all_true()

Returns true if the stack is empty or all the contained elements are True

flip()

Toggle the following element

pop()

Pop element from the stack

push(v_element)

Push element to the stack

add_path(path)

Add a new path to the search directory list so that HDLMake will search for found includes on it

get_file_deps()

Look for all of the defined preprocessor filedeps and return a list containing all of them

preprocess(vlog_file)

Assign the provided ‘vlog_file’ to the associated class property and then preprocess and return the Verilog code

vpp_keywords = ['default_nettype', 'define', 'line', 'include', 'elsif', 'ifdef', 'endif', 'else', 'undef', 'timescale']

Module contents

This file is the entry point for the complete HDLMake package