hdlmake.tools.libero package

Module contents

Module providing support for Microsemi Libero IDE synthesis

class hdlmake.tools.libero.ToolLibero

Bases: hdlmake.tools.make_syn.ToolSyn

Class providing the interface for Microsemi Libero IDE synthesis

CLEAN_TARGETS = {'clean': ['$(PROJECT)'], 'mrproper': ['*.pdb', '*.stp']}

HDL_FILES = {<class 'hdlmake.srcfile.VHDLFile'>: 'create_links -hdl_source {$$filename}', <class 'hdlmake.srcfile.VerilogFile'>: 'create_links -hdl_source {$$filename}'}

STANDARD_LIBS = ['ieee', 'std']

SUPPORTED_FILES = {<class 'hdlmake.srcfile.PDCFile'>: 'create_links -pdc {$$filename}', <class 'hdlmake.srcfile.SDCFile'>: 'create_links -sdc {$$filename}'}

TCL_CONTROLS = {'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb', 'bitstream': '$(TCL_OPEN)\nupdate_and_run_tool -name {GENERATEPROGRAMMINGDATA}\n$(TCL_SAVE)\n$(TCL_CLOSE)', 'create': 'new_project -location {{./{0}}} -name {{{0}}} -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}} -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}', 'project': '$(TCL_CREATE)\n$(TCL_FILES)\n{0}\n$(TCL_SAVE)\n$(TCL_CLOSE)', 'close': 'close_project', 'save': 'save_project', 'open': 'open_project -file {$(PROJECT)/$(PROJECT_FILE)}'}

TOOL_INFO = {'linux_bin': 'libero SCRIPT:', 'windows_bin': 'libero.exe SCRIPT:', 'project_ext': 'prjx', 'name': 'Libero', 'id': 'libero'}