srcfile module

class srcfile.BDFile(path, module=None)

Bases: dep_file.File

class srcfile.CDCFile(path, module=None)

Bases: dep_file.File

class srcfile.DPFFile(path, module=None)

Bases: dep_file.File

class srcfile.EDFFile(path, module=None)

Bases: dep_file.File

class srcfile.LDFFile(path, module=None)

Bases: dep_file.File

class srcfile.LPFFile(path, module=None)

Bases: dep_file.File

class srcfile.NGCFile(path, module=None)

Bases: dep_file.File

class srcfile.PDCFile(path, module=None)

Bases: dep_file.File

class srcfile.PPRFile(path, module=None)

Bases: dep_file.File

class srcfile.QIPFile(path, module=None)

Bases: dep_file.File

class srcfile.SDCFile(path, module=None)

Bases: dep_file.File

class srcfile.SVFile(path, module, library=None, vlog_opt=None, include_dirs=None)

Bases: srcfile.VerilogFile

class srcfile.SignalTapFile(path, module=None)

Bases: dep_file.File

class srcfile.SourceFile(path, module, library=None)

Bases: dep_file.DepFile

cur_index = 0

class srcfile.SourceFileFactory

new(path, module, library=None, vcom_opt=None, vlog_opt=None, include_dirs=None)

class srcfile.SourceFileSet

Bases: set

add(files)

filter(type)

get_libs()

inversed_filter(type)

class srcfile.TCLFile(path, module=None)

Bases: dep_file.File

class srcfile.UCFFile(path, module=None)

Bases: dep_file.File

class srcfile.VHDLFile(path, module, library=None, vcom_opt=None)

Bases: srcfile.SourceFile

class srcfile.VerilogFile(path, module, library=None, vlog_opt=None, include_dirs=None)

Bases: srcfile.SourceFile

class srcfile.WBGenFile(path, module=None)

Bases: dep_file.File

class srcfile.XCOFile(path, module=None)

Bases: dep_file.File

class srcfile.XISEFile(path, module=None)

Bases: dep_file.File

class srcfile.XMPFile(path, module=None)

Bases: dep_file.File

class srcfile.XPRFile(path, module=None)

Bases: dep_file.File